stm32n6: Add sys_get_reset_reason() backed by RCC_RSR

Mirror the pattern used by the other stm32 ports. Reads RCC_RSR once
in an early constructor, maps the STM32N6-specific flags to the
portable reset_reason_t bits, and clears the flags via RMVF so the
next boot reflects only the new cause. The sysinfo shell command
then prints the cause on reboot like it does on h7/g4/f4.

Reset-reason bits from RM0486 §14.10.8 (RCC_RSR):
  bit 30 LPWRRSTF → LOW_POWER_RESET
  bit 28 WWDGRSTF → WATCHDOG
  bit 26 IWDGRSTF → WATCHDOG
  bit 24 SFTRSTF  → SW_RESET
  bit 23 PORRSTF  → POWER_ON
  bit 22 PINRSTF  → EXT_RESET
  bit 21 BORRSTF  → BROWNOUT
  bit 17 LCKRSTF  → CPU_LOCKUP

Author: andoma

src/platform/stm32n6/stm32n6.mk

@@ -25,6 +25,7 @@ SRCS += ${C}/systick.c \
 	${P}/stm32n6_dma.c \
 	${P}/stm32n6_rif.c \
 	${P}/stm32n6_idle.c \
+	${P}/stm32n6_info.c \
 
 SRCS-${ENABLE_NET_IPV4} += ${P}/stm32n6_eth.c
 

src/platform/stm32n6/stm32n6_clk.h

@@ -8,6 +8,7 @@
 #define RCC_SR            (RCC_BASE + 0x004)
 #define RCC_CFGR1         (RCC_BASE + 0x020)
 #define RCC_CFGR2         (RCC_BASE + 0x024)
+#define RCC_RSR           (RCC_BASE + 0x034)
 
 #define RCC_PLLxCFGR1(x)  (RCC_BASE + 0x70 + (x) * 0x10)
 #define RCC_PLLxCFGR2(x)  (RCC_BASE + 0x74 + (x) * 0x10)

src/platform/stm32n6/stm32n6_info.c

@@ -0,0 +1,60 @@
+#include <mios/sys.h>
+
+#include "stm32n6_reg.h"
+#include "stm32n6_clk.h"
+
+// RCC_RSR bit layout (RM0486 §14.10.8):
+//   bit 30 LPWRRSTF  — Illegal Stop or Standby
+//   bit 28 WWDGRSTF  — Window watchdog reset
+//   bit 26 IWDGRSTF  — Independent watchdog reset
+//   bit 24 SFTRSTF   — Software reset (SYSRESETREQ)
+//   bit 23 PORRSTF   — POR/PDR
+//   bit 22 PINRSTF   — Pin (NRST) reset
+//   bit 21 BORRSTF   — Brownout reset
+//   bit 17 LCKRSTF   — CPU lockup
+//   bit 16 RMVF      — write-1 to clear all flags
+
+#define RCC_RSR_LPWRRSTF  (1u << 30)
+#define RCC_RSR_WWDGRSTF  (1u << 28)
+#define RCC_RSR_IWDGRSTF  (1u << 26)
+#define RCC_RSR_SFTRSTF   (1u << 24)
+#define RCC_RSR_PORRSTF   (1u << 23)
+#define RCC_RSR_PINRSTF   (1u << 22)
+#define RCC_RSR_BORRSTF   (1u << 21)
+#define RCC_RSR_LCKRSTF   (1u << 17)
+#define RCC_RSR_RMVF      (1u << 16)
+
+static uint32_t reset_reason;
+
+static void __attribute__((constructor(102)))
+stm32n6_get_reset_reason(void)
+{
+  uint32_t rr = reg_rd(RCC_RSR);
+  uint32_t n = 0;
+
+  if(rr & RCC_RSR_LPWRRSTF)
+    n |= RESET_REASON_LOW_POWER_RESET;
+  if(rr & (RCC_RSR_IWDGRSTF | RCC_RSR_WWDGRSTF))
+    n |= RESET_REASON_WATCHDOG;
+  if(rr & RCC_RSR_SFTRSTF)
+    n |= RESET_REASON_SW_RESET;
+  if(rr & RCC_RSR_PORRSTF)
+    n |= RESET_REASON_POWER_ON;
+  if(rr & RCC_RSR_PINRSTF)
+    n |= RESET_REASON_EXT_RESET;
+  if(rr & RCC_RSR_BORRSTF)
+    n |= RESET_REASON_BROWNOUT;
+  if(rr & RCC_RSR_LCKRSTF)
+    n |= RESET_REASON_CPU_LOCKUP;
+
+  // Clear the flags so the next boot shows only the new cause
+  reg_wr(RCC_RSR, RCC_RSR_RMVF);
+
+  reset_reason = n;
+}
+
+reset_reason_t
+sys_get_reset_reason(void)
+{
+  return reset_reason;
+}