if interested here the info about my i5-14600K ----> ./corefreq-cli -s -n -m -n -i 1 -n -c 1 -n -g 1 -n -C 1 -n -M #583

disgorge69 · 2026-03-21T10:33:22Z

disgorge69
Mar 21, 2026


Processor                                          [Intel(R) Core(TM) i5-14600K]
|- Architecture                                                    [Raptor Lake]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x00000133]
|- Signature                                                           [  06_B7]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 20/ 20]
|- Base Clock                                                          [ 99.840]
|- Frequency            (MHz)                      Ratio                        
                 Min    798.72                    <   8 >                       
                 Max   3494.38                    <  35 >                       
|- Factory                                                             [100.000]
                       3500                       [  35 ]                       
|- Overclock                                                           [ UNLOCK]
                 Bin   +700                       [  +7 ]                       
|- Performance                                                                  
                 TGT   1098.23                    <  11 >                       
   |- HWP                                                                       
                 Min    798.71                    <   8 >                       
                 Max   6988.77                    <  70 >                       
                 TGT      AUTO                    <   0 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   5491.17                    <  55 >                       
                  2C   5491.17                    <  55 >                       
                  3C   5491.17                    <  55 >                       
                  4C   5491.17                    <  55 >                       
                  5C   5491.17                    <  55 >                       
                  6C   5491.17                    <  55 >                       
                  7C   5491.17                    <  55 >                       
                  8C   5491.17                    <  55 >                       
|- Hybrid                                                              [ UNLOCK]
                  1C   4093.34                    <  41 >                       
                  2C   4093.34                    <  41 >                       
                  3C   4093.34                    <  41 >                       
                  4C   4093.34                    <  41 >                       
                  5C   4093.34                    <  41 >                       
                  6C   4093.34                    <  41 >                       
                  7C   4093.34                    <  41 >                       
                  8C   4093.34                    <  41 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    798.70                    <   8 >                       
                 Max   3993.50                    <  40 >                       
|- TDP                                                           Level [  0:3  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   3494.38                    [  35 ]                       
               Turbo      AUTO                    <   0 >                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AMX-BF16     [N]     AMX-TILE [N]     AMX-INT8 [N]    AMX-FP16 [N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N] 
|- AVX-IFMA     [N]    CMPccXADD [N]      MOVDIRI [Y]   MOVDIR64B [Y] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- ENQCMD       [N]         GFNI [Y]        OSPKE [Y]     WAITPKG [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [Y]      SYSCALL [Y]        RDPID [Y]         SGX [N] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB|SCASB                                   FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                            FMA   [Capable]
|- Flexible Return and Event Delivery                           FRED   [Missing]
|- Hardware Feedback Interface                                   HFI   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- History Reset                                              HRESET   [Capable]
|- Hybrid part processor                                      HYBRID   [Capable]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Space Separation                              LASS   [Missing]
|- Linear Address Masking                                        LAM   [Missing]
|- Load Kernel GS segment register                              LKGS   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Capable]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Write Data to a Processor Trace Packet                    PTWRITE   [Capable]
|- PREFETCHIT0/1 Instructions                              PREFETCHI   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [ Enable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Enable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [ Enable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [ Enable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [Capable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Capable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [ Enable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [ Enable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [ Enable]
|- Arch - STLB QoS                                              STLB   [ Enable]
|- Arch - Functional Safety Island                              FuSa   [ Enable]
|- Arch - RSM in CPL0 only                                       RSM   [ Enable]
|- Arch - Split Locked Access Exception                         SPLA   [ Enable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Enable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [Capable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [ Enable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [ Enable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Capable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [ Unable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [ Unable]
   |- Restricted Transactional Memory                            RTM   [ Unable]
   |- Verify Segment for Writing instruction                    VERW   [ Unable]
|- Arch - Restricted RSB Alternate                             RRSBA   [ Enable]
|- Arch - No Branch Target Injection                          BHI_NO   [Capable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Capable]
|- Arch - No Gather Data Sampling                             GDS_NO   [ Enable]
|- Arch - No Register File Data Sampling                     RFDS_NO   [Capable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [Capable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [Capable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [Capable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [Capable]
|- Arch - Data Dependent Prefetcher CPL3                  DDPD_U_DIS   [Capable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [ Enable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
|- No MONITOR/UMONITOR mitigation                       UMON_MITG_NO   [Capable]
|- Overclocking                                                                 
   |- Overclocking Utilized                                 UTILIZED   [ Enable]
   |- Undervolt Protection                                       UVP   [ Enable]
   |- Overclocking Secure Status                            UNLOCKED   [Capable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Capable]
|- AES Key Locker instructions                                AESKLE   [Missing]
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- CET Indirect Branch Tracking                              CET-IBT   [Capable]
|- CET Supervisor Shadow Stack                               CET-SSS   [Capable]
|- AES Wide Key Locker instructions                          WIDE_KL   [Capable]
|- Software Guard SGX1 Extensions                               SGX1   [Missing]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   <OFF>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L1 Next Page Prefetcher                                     L1 NPP   <OFF>
   |- L1 Scrubbing                                          L1 Scrubbing   <OFF>
|- Cache Prefetchers                                                            
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Adjacent Cache Line Prefetcher                         L2 HW CL   < ON>
   |- L2 Adaptive Multipath Probability                           L2 AMP   <OFF>
   |- L2 Next Line Prefetcher                                     L2 NLP   <OFF>
   |- LLC Streamer                                                   LLC   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         4.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
|- Volume Management Device                                          VMD   [ ON]
|- Gaussian & Neural Accelerator                                     GNA   [ ON]
|- Digital Content Protection                                       HDCP   [ ON]
|- Image Processing Unit                                             IPU   [OFF]
|- Vision Processing Unit                                            VPU   [OFF]
|- Overclocking                                                       OC   [ ON]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  5]
|- Counters:          General                   Fixed                           
|           {  6,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       [N/A]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C1>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- ACPI Processor C-States                                      _CST   [      2]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     0     1     0     1              
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [     13]
|- Performance Present Capabilities                             _PPC   [      0]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:100 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
   |- Energy Policy                                          HWP EPP   <    128>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [  125 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  220 W>
   |- Time Window                                                TW1   <   56 s>
   |- Power Limit                                                PL2   <  220 W>
   |- Time Window                                                TW2   <   2 ms>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   <   28 s>
   |- Power Limit                                                PL2   <    0 W>
   |- Time Window                                                TW2   < 976 us>
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID  Hybrid ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0  P   1   0  0   32768  8     49152 12   2097152 16  25165824 12  
001:  0    1  P   1   0  1   32768  8     49152 12   2097152 16  25165824 12  
002:  0    8  P   1   4  0   32768  8     49152 12   2097152 16  25165824 12  
003:  0    9  P   1   4  1   32768  8     49152 12   2097152 16  25165824 12  
004:  0   16  P   1   8  0   32768  8     49152 12   2097152 16  25165824 12  
005:  0   17  P   1   8  1   32768  8     49152 12   2097152 16  25165824 12  
006:  0   24  P   1  12  0   32768  8     49152 12   2097152 16  25165824 12  
007:  0   25  P   1  12  1   32768  8     49152 12   2097152 16  25165824 12  
008:  0   32  P   1  16  0   32768  8     49152 12   2097152 16  25165824 12  
009:  0   33  P   1  16  1   32768  8     49152 12   2097152 16  25165824 12  
010:  0   40  P   1  20  0   32768  8     49152 12   2097152 16  25165824 12  
011:  0   41  P   1  20  1   32768  8     49152 12   2097152 16  25165824 12  
012:  0   48  E   1  24  0   65536  8     32768  8   4194304 16  25165824 12  
013:  0   50  E   1  25  0   65536  8     32768  8   4194304 16  25165824 12  
014:  0   52  E   1  26  0   65536  8     32768  8   4194304 16  25165824 12  
015:  0   54  E   1  27  0   65536  8     32768  8   4194304 16  25165824 12  
016:  0   56  E   1  28  0   65536  8     32768  8   4194304 16  25165824 12  
017:  0   58  E   1  29  0   65536  8     32768  8   4194304 16  25165824 12  
018:  0   60  E   1  30  0   65536  8     32768  8   4194304 16  25165824 12  
019:  0   62  E   1  31  0   65536  8     32768  8   4194304 16  25165824 12  

CPU     IPS            IPC            CPI
000     0.002015/s     0.189539/c     5.275952/i
001     0.000213/s     0.075043/c    13.325684/i
002     0.001734/s     0.210022/c     4.761395/i
003     0.000043/s     0.069007/c    14.491211/i
004     0.003927/s     0.189203/c     5.285333/i
005     0.000124/s     0.071901/c    13.908026/i
006     0.000969/s     0.087660/c    11.407703/i
007     0.004386/s     0.104010/c     9.614505/i
008     0.003101/s     0.159714/c     6.261201/i
009     0.000305/s     0.215675/c     4.636611/i
010     0.003904/s     0.174420/c     5.733291/i
011     0.000545/s     0.142669/c     7.009238/i
012     0.001286/s     0.077250/c    12.944927/i
013     0.000587/s     0.081270/c    12.304628/i
014     0.000529/s     0.079643/c    12.556055/i
015     0.000109/s     0.069244/c    14.441695/i
016     0.000105/s     0.070108/c    14.263650/i
017     0.000138/s     0.058885/c    16.982147/i
018     0.000145/s     0.058353/c    17.137087/i
019     0.000036/s     0.062326/c    16.044716/i


CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000    3.81 ( 0.04)   0.11   0.50   1.66   0.00  97.68   0.00  24 / 25:75 / 30
001    1.87 ( 0.02)   0.05   0.23   1.66   0.00  97.68   0.00  24 / 25:75 / 30
002   19.51 ( 0.20)   0.56   1.96  11.29   0.00  86.70   0.00  23 / 24:76 / 30
003    0.45 ( 0.00)   0.01   0.06  11.29   0.00  86.70   0.00  23 / 24:76 / 30
004    4.42 ( 0.04)   0.13   0.56   0.06   0.00  99.25   0.00  23 / 24:76 / 28
005    1.62 ( 0.02)   0.05   0.18   0.06   0.00  99.25   0.00  23 / 24:76 / 28
006    8.16 ( 0.08)   0.23   1.16   0.48   0.00  93.35   0.00  24 / 24:76 / 35
007   50.65 ( 0.51)   1.45   5.09   0.48   0.00  93.35   0.00  24 / 24:76 / 35
008   16.13 ( 0.16)   0.46   1.68   3.14   0.00  95.04   0.00  22 / 23:77 / 44
009    1.22 ( 0.01)   0.04   0.14   3.14   0.00  95.04   0.00  22 / 23:77 / 44
010   19.22 ( 0.19)   0.55   1.89  18.65   0.00  79.40   0.00  19 / 23:77 / 25
011    0.69 ( 0.01)   0.02   0.09  18.65   0.00  79.40   0.00  19 / 23:77 / 25
012   10.76 ( 0.11)   0.31   1.47   1.45   0.00  96.62   0.00  24 / 25:75 / 33
013    3.84 ( 0.04)   0.11   0.53   0.00   0.00  99.25   0.00  24 / 25:75 / 33
014    4.86 ( 0.05)   0.14   0.66   1.37   0.00  97.78   0.00  24 / 25:75 / 33
015    1.05 ( 0.01)   0.03   0.15   0.00   0.00  99.76   0.00  24 / 25:75 / 33
016    0.77 ( 0.01)   0.02   0.11   0.00   0.00  99.82   0.00  24 / 25:75 / 28
017    1.61 ( 0.02)   0.05   0.23   0.03   0.00  99.63   0.00  24 / 25:75 / 28
018    1.77 ( 0.02)   0.05   0.25   0.00   0.00  99.61   0.00  24 / 25:75 / 28
019    0.42 ( 0.00)   0.01   0.06   0.00   0.00  99.91   0.00  24 / 25:75 / 28

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                      0.22   0.85   3.67   0.00  94.76   0.00     100 C    29 C


		Cycles		State(%)
PC02	                 0	   0.00
PC03	                 0	   0.00
PC04	                 0	   0.00
PC06	                 0	   0.00
PC07	                 0	   0.00
PC08	                 0	   0.00
PC09	                 0	   0.00
PC10	                 0	   0.00
MC6	        3126547515	  91.84
PTSC	        3494333166
UNCORE	         981003318


CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   23.12  5939  0.7250   27  000000000000000000    0.000000000   0.000000000
001    3.40     0  0.0000   27  000000000000000000    0.000000000   0.000000000
002   34.32  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
003    0.56     0  0.0000   25  000000000000000000    0.000000000   0.000000000
004   25.81  5939  0.7250   24  000000000000000000    0.000000000   0.000000000
005    1.24     0  0.0000   24  000000000000000000    0.000000000   0.000000000
006   49.42  5939  0.7250   27  000000000000000000    0.000000000   0.000000000
007   35.64     0  0.0000   27  000000000000000000    0.000000000   0.000000000
008   64.15  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
009   38.40     0  0.0000   25  000000000000000000    0.000000000   0.000000000
010   89.20  5939  0.7250   22  000000000000000000    0.000000000   0.000000000
011    0.61     0  0.0000   22  000000000000000000    0.000000000   0.000000000
012   73.60  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
013   62.12  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
014   55.97  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
015   45.91  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
016    5.96  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
017    4.20  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
018    5.40  5939  0.7250   25  000000000000000000    0.000000000   0.000000000
019    7.93  5939  0.7250   25  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   8.388183594   7.039794922   0.000000000   0.000000000   0.000000000
Power(W) :   8.388183594   7.039794922   0.000000000   0.000000000   0.000000000


                             Intel Z690  [7A84]                            
Controller #0                                                Dual Channel  
 Bus Rate  4000 MHz       Bus Speed 3993 MHz           DDR4 Speed 7987 MT/s
                                                                           
 Cha    CL RCDr RCDw   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL  CKE  CMD
  #0    18   22   22   22   38   10   15   18   24   12   48   20    8   2T
  #1     0    0    0    0    0    0    0    0    0    0    0    0    0   0T
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     8    4   12   12        15   15   15   15        38   31    9    9
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                REFI  RFC  XS   XP CPDED GEAR  ECC
  #0     8    4   13   13               20500  670  688   11    4    1    0
  #1     0    0    0    0                   0    0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          32768  TEAMGROUP-UD4-3600
                                                                           
Controller #1                                                Dual Channel  
 Bus Rate  4000 MHz       Bus Speed 3993 MHz           DDR4 Speed 7987 MT/s
                                                                           
 Cha    CL RCDr RCDw   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL  CKE  CMD
  #0    18   22   22   22   38   10   15   18   24   12   48   20    8   2T
  #1     0    0    0    0    0    0    0    0    0    0    0    0    0   0T
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     8    4   12   12        15   15   15   15        38   31    9    9
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                REFI  RFC  XS   XP CPDED GEAR  ECC
  #0     8    4   13   13               20500  670  688   11    4    1    0
  #1     0    0    0    0                   0    0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          32768  TEAMGROUP-UD4-3600

cyring · 2026-03-21T11:33:25Z

cyring
Mar 21, 2026
Maintainer

if interested here the info about my i5-14600K

Sure! Thank you very much. Now part of Wiki

1 reply

disgorge69 Mar 21, 2026
Author

Pleasure

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

if interested here the info about my i5-14600K ----> ./corefreq-cli -s -n -m -n -i 1 -n -c 1 -n -g 1 -n -C 1 -n -M #583

Uh oh!

{{title}}

Uh oh!

Replies: 1 comment 1 reply

Uh oh!

{{title}}

Uh oh!

Uh oh!

{{title}}

Uh oh!

Select a reply

Uh oh!

if interested here the info about my i5-14600K ----> ./corefreq-cli -s -n -m -n -i 1 -n -c 1 -n -g 1 -n -C 1 -n -M #583

Uh oh!

disgorge69 Mar 21, 2026

Replies: 1 comment · 1 reply

Uh oh!

cyring Mar 21, 2026 Maintainer

Uh oh!

disgorge69 Mar 21, 2026 Author

disgorge69
Mar 21, 2026

Replies: 1 comment 1 reply

cyring
Mar 21, 2026
Maintainer

disgorge69 Mar 21, 2026
Author