Hi and congratulations on your project.
I was wondering if this discussion might be of your interest:
ghdl/ghdl#1519
Do you think that it could make sense to parse the dumps produced by GHDL and represent it using your library? Or maybe the netlist generated by GHDL synthesis?
I was trying to understand what could be the most simple, easiest and efficient way to generate a simple schematic starting from a VHDL source file. We have the dumps, we have the parsers, we have the layout and schematic generation tools, the only thing needed is to put them together. I was trying to estimate the possible effort of doing this, in terms of time needed.
Hi and congratulations on your project.
I was wondering if this discussion might be of your interest:
ghdl/ghdl#1519
Do you think that it could make sense to parse the dumps produced by GHDL and represent it using your library? Or maybe the netlist generated by GHDL synthesis?
I was trying to understand what could be the most simple, easiest and efficient way to generate a simple schematic starting from a VHDL source file. We have the dumps, we have the parsers, we have the layout and schematic generation tools, the only thing needed is to put them together. I was trying to estimate the possible effort of doing this, in terms of time needed.