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‎application-processors.html‎

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<div id="content" class="content">
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<main>
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<h2 id="application-processors"><a class="header" href="#application-processors">Application Processors</a></h2>
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<h1 id="application-processors"><a class="header" href="#application-processors">Application Processors</a></h1>
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<p>An <em>Application Processor</em> (AP) is the main processing unit of a system,
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commonly designed as a <em>System on Chip</em> (SoC). APs are sometimes also considered
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microprocessors, as opposed to microcontrollers. Another regularly used term is
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<em>Central Processing Unit</em> (CPU). While design approaches and names have changed
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over the years, psi-spec is concerned with the kind of processors that feature a
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<em>Memory Management Unit</em> (MMU) and DRAM, allowing for many concurrent tasks and
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processing large amounts of data.</p>
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<h3 id="system-on-chip"><a class="header" href="#system-on-chip">System on Chip</a></h3>
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<p>An SoC integrates application processing units with <a href="./peripherals">peripherals</a>
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via internal system buses, all packaged into one chip. Common buses are defined
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by the <a href="https://developer.arm.com/Architectures/AMBA">AMBA</a> standards and the
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<a href="https://opencores.org/howto/wishbone">WISHBONE Interconnect Architecture</a>. Some
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vendors have their own designs, such as AMD's <a href="https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/other/56978.pdf">Infinity Fabric</a>.
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A bus is generally a set of physical interfaces and corresponding protocols.
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Parts of an SoC are called blocks.</p>
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<h2 id="system-on-chip"><a class="header" href="#system-on-chip">System on Chip</a></h2>
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<p>An SoC integrates processing units with IO <a href="peripherals.html">peripherals</a> via
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internal system buses and networks, all packaged into one chip.</p>
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<p>Common buses are defined by the
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<a href="https://developer.arm.com/Architectures/AMBA">AMBA</a> standards, the
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<a href="https://opencores.org/howto/wishbone">WISHBONE Interconnect Architecture</a>, and
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<a href="https://en.wikipedia.org/wiki/CoreConnect">CoreConnect</a>.
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Some vendors have their own designs, such as AMD's <a href="https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/other/56978.pdf">Infinity Fabric</a>.
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A bus is generally a set of physical interfaces and corresponding protocols.</p>
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<p>A <a href="https://en.wikipedia.org/wiki/Network_on_a_chip">Network on a Chip (NoC)</a>
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improves the scalability of SoC components and its power efficiency over shared
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buses.</p>
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<p>Parts of an SoC are called blocks.</p>
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<p><img src="images/simple-soc.png" alt="logical view of a simple SoC" /></p>
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</main>

‎boot-environments.html‎

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<div id="content" class="content">
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<main>
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<h2 id="boot-environments"><a class="header" href="#boot-environments">Boot Environments</a></h2>
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<h1 id="boot-environments"><a class="header" href="#boot-environments">Boot Environments</a></h1>
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<p>A <em>boot environment</em> is the hosting system of a <em>boot loader</em>.</p>
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<p>Boot processes may be interactive, or automatic, or static, set up in many ways.</p>
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<p>The following table classifies various approaches with example implementations.</p>

‎index.html‎

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<div id="content" class="content">
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<main>
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<h2 id="introduction"><a class="header" href="#introduction">Introduction</a></h2>
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<h1 id="introduction"><a class="header" href="#introduction">Introduction</a></h1>
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<p><img src="images/logo.svg" alt="PSI logo" /></p>
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<p>The Platform System Interface Specification, or <em>psi-spec</em>, is
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a collection of documents for <a href="#">hardware and software co-design</a> from a general perspective.
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It describes how <a href="./application-processors">microprocessors</a> provide an
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a collection of documents for [hardware and software co-design](</p>
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<h1 id="-from-a-general-perspective"><a class="header" href="#-from-a-general-perspective">) from a general perspective.</a></h1>
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<p>It describes how <a href="./application-processors">microprocessors</a> provide an
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<a href="boot-environments.html">environment for booting</a> operating systems or otherwise
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bare-metal applications, typically starting from intermediate, rewritable code
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that initializes clocks, DRAM and peripherals, commonly referred to as boot

‎intro.html‎

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<div id="content" class="content">
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<main>
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<h2 id="introduction"><a class="header" href="#introduction">Introduction</a></h2>
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<h1 id="introduction"><a class="header" href="#introduction">Introduction</a></h1>
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<p><img src="images/logo.svg" alt="PSI logo" /></p>
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<p>The Platform System Interface Specification, or <em>psi-spec</em>, is
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a collection of documents for <a href="#">hardware and software co-design</a> from a general perspective.
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It describes how <a href="./application-processors">microprocessors</a> provide an
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a collection of documents for [hardware and software co-design](</p>
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<h1 id="-from-a-general-perspective"><a class="header" href="#-from-a-general-perspective">) from a general perspective.</a></h1>
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<p>It describes how <a href="./application-processors">microprocessors</a> provide an
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<a href="boot-environments.html">environment for booting</a> operating systems or otherwise
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bare-metal applications, typically starting from intermediate, rewritable code
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that initializes clocks, DRAM and peripherals, commonly referred to as boot

‎mask-roms-loaders.html‎

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<div id="content" class="content">
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<main>
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<h2 id="mask-roms-and-loaders"><a class="header" href="#mask-roms-and-loaders">Mask ROMs and Loaders</a></h2>
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<h1 id="mask-roms-and-loaders"><a class="header" href="#mask-roms-and-loaders">Mask ROMs and Loaders</a></h1>
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<p>Many SoCs have initial pieces of code baked into them to bootstrap the system.
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Some may call them boot ROMs, otherwise known as mask ROMs or Zero Stage Boot
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Loaders (ZSBL). They define a low-level access channel for development and would
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of such a mechanism, they also have their own software utilities that understand
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the respective protocol. With that software, one may read out chip information,
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perform MMIO access, transfer data into memory and execute it, set fuses, etc.</p>
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<h3 id="generic-protocols-variants-and-tools"><a class="header" href="#generic-protocols-variants-and-tools">Generic protocols, variants and tools</a></h3>
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<h2 id="generic-protocols-variants-and-tools"><a class="header" href="#generic-protocols-variants-and-tools">Generic protocols, variants and tools</a></h2>
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<ul>
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<li><a href="https://www.usb.org/document-library/device-firmware-upgrade-11-new-version-31-aug-2004">USB Device Firmware Upgrade (DFU)</a>
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<ul>
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</ul>
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</li>
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</ul>
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<h3 id="vendor-specific-protocols-and-tools"><a class="header" href="#vendor-specific-protocols-and-tools">Vendor specific protocols and tools</a></h3>
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<h2 id="vendor-specific-protocols-and-tools"><a class="header" href="#vendor-specific-protocols-and-tools">Vendor specific protocols and tools</a></h2>
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<ul>
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<li>Allwinner: FEL mode, usable with
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<ul>

‎peripherals.html‎

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<div id="content" class="content">
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<main>
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<h2 id="peripherals"><a class="header" href="#peripherals">Peripherals</a></h2>
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<h1 id="peripherals"><a class="header" href="#peripherals">Peripherals</a></h1>
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<p>Systems connect with external hardware components, also known as <em>peripherals</em>,
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using buses and controllers. A controller is a unit driving a bus, such as the
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high-speed USB and PCIe buses or the slower SPI and I2C. Hardware platforms may

‎platform-initialization.html‎

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<div id="content" class="content">
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<main>
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<h2 id="platform-initialization"><a class="header" href="#platform-initialization">Platform Initialization</a></h2>
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<h1 id="platform-initialization"><a class="header" href="#platform-initialization">Platform Initialization</a></h1>
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<p>Booting a rich, virtual memory operating system poses challenges. While modern
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machines may offer gigabytes or even terabytes of <em>dynamic random access memory</em>
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<a href="https://en.wikipedia.org/wiki/Dynamic_random-access_memory">DRAM</a> and extremely
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controllers as needed to load and boot an operating system. Due to the high
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diversity of hardware, every SoC, SoM and mainboard comes with specific
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necessities.</p>
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<h3 id="boot-flows"><a class="header" href="#boot-flows">Boot Flows</a></h3>
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<h2 id="boot-flows"><a class="header" href="#boot-flows">Boot Flows</a></h2>
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<p>Since memory and storage parts can be complex, additional firmware and loaders
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are implemented in software. They would initialize the platform step by step,
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phase by phase, or stage by stage; projects differ in naming.</p>
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</tbody></table>
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</div>
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<p><strong>Note</strong>:
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<a href="https://github.com/oreboot/oreboot/tree/main/Documentation/boot-flow.md">oreboot
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</a> and
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<a href="https://github.com/oreboot/oreboot/tree/main/Documentation/boot-flow.md">oreboot</a>
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and
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<a href="https://doc.coreboot.org/getting_started/architecture.html">coreboot</a> do not
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implement boot loaders to access external storage themselves. Instead, they
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provide options for payloads that could load a final OS or stand for themselves;
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unless ways to circumvent the verification are found. This is also true for many
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OEM products in general, where custom firmware is not part of the product
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design. I.e., it is <a href="platform-security.html">protected against modification</a>.</p>
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<h3 id="references"><a class="header" href="#references">References</a></h3>
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<h4 id="arm-platforms"><a class="header" href="#arm-platforms">Arm platforms</a></h4>
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<h2 id="references"><a class="header" href="#references">References</a></h2>
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<h3 id="arm-platforms"><a class="header" href="#arm-platforms">Arm platforms</a></h3>
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<ul>
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<li><a href="https://youtu.be/GXFw8SV-51g">How Arm systems are booted</a></li>
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<li><a href="https://youtu.be/u0-swEMDFp0">U-Boot / Amlogic</a></li>
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</ul>
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</li>
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<h4 id="risc-v-platforms"><a class="header" href="#risc-v-platforms">RISC-V platforms</a></h4>
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<p><strong>TODO</strong></p>
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<h3 id="risc-v-platforms"><a class="header" href="#risc-v-platforms">RISC-V platforms</a></h3>
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<p>TODO</p>
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</main>
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‎platform-security.html‎

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<main>
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<h2 id="platform-security"><a class="header" href="#platform-security">Platform Security</a></h2>
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<h1 id="platform-security"><a class="header" href="#platform-security">Platform Security</a></h1>
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<p>In order to design a secure platform, each and every component in the boot
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process must be <em>measured</em> and/or <em>verified</em>. In addition, the platform in its
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entirety must be modeled so that only desired operations are permitted.</p>

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