[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735
[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735KornevNikita merged 4 commits intointel:syclfrom
Conversation
premanandrao
force-pushed
the
remote_fpga_pr3
branch
from
7dd0d8e to
a0f55f0
Compare
| let PragmaAttributeSupport = 0; | ||
| } | ||
|
|
||
| def SYCLIntelIVDep : StmtAttr { |
There was a problem hiding this comment.
I was curious about what ivdep is and google gave me this https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/developer-guide/2025-0/ivdep-attribute.html . I wonder if need to ask someone to remove this from somewhere too
| return LHS->getSafelenValue() > RHS->getSafelenValue(); | ||
| } | ||
| }]; | ||
| let Documentation = [SYCLIntelIVDepAttrDocs]; |
There was a problem hiding this comment.
Wait, should we also remove all the docs?
There was a problem hiding this comment.
Thanks, I removed from AttrDocs.td. I will go back and see if I missed removing any from the previous two PRs; and if it is from the merged one, will create a new PR for that.
Fznamznon
left a comment
Fznamznon
left a comment
There was a problem hiding this comment.
Requesting changes so we don't miss docs removal
premanandrao
force-pushed
the
remote_fpga_pr3
branch
from
06d5604 to
6a25edb
Compare
|
@premanandrao could you please resolve the merge conflicts |
|
@intel/llvm-gatekeepers please consider merging |
premanandrao
force-pushed
the
remote_fpga_pr3
branch
from
6a25edb to
3f1499d
Compare
3 participants
This removes the following attributes:
[[intel::ivdep]]
[[intel::initiation_interval]]
[[intel::ii]]
[[intel::max_concurrency]]
[[intel::speculated_iterations]]
[[intel::max_reinvocation_delay]]
[[intel::disable_loop_pipelining]]
[[intel::enable_loop_pipelining]]