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jangam-ajay/README.md

👋 Hi, I'm Ajay Jangam!

💼 Physical Design Engineer
🎓 Electronics & Communication Engineer

💡 Passionate about RTL-to-GDSII flow, STA, ECO, and physical design sign-off
🚀 Hands-on experience with Cadence (Genus, Innovus, Tempus) & Synopsys (DC, ICC2, PrimeTime, StarRC)
📚 Working across 28nm, 32nm & 45nm nodes | Learning low-power design & TCL automation

🔗 Connect with me

📧 ajayjangam317@gmail.com
💼 https://linkedin.com/in/jangamajay
🐙 https://github.com/jangam-ajay

📌 Pinned Projects

🔹 ORCA TOP — 32-bit RISC Core Processor
28nm | 435 MHz | Synopsys ICC2 + StarRc +PrimeTime

🔹 CHIP TOP — Multi-Channel Memory Controller
45nm | 200 MHz | Cadence Innovus + Tempus

🔹 Electronic Voting Machine
FPGA Implementation | Verilog | Xilinx Vivado

💻 Tech Stack

Cadence Innovus Cadence Genus Cadence Tempus
Synopsys ICC2 Synopsys PrimeTime StarRC Design Compiler
TCL Scripting Verilog HDL Linux
DEF LEF SPEF GDSII

🎯 Open to Opportunities

Actively looking for Physical Design / VLSI Backend Engineer roles

Pinned Loading

  1. VLSI_PD_ORCA_TOP VLSI_PD_ORCA_TOP Public

    PD_ORCA_TOP_28nm demonstrated a complete block-level ASIC PnR flow using Synopsys ICC2, transforming gate-level netlist to GDSII across floorplanning, power planning, placement, CTS, routing, and s…

    Tcl 1 1

  2. CHIP_TOP CHIP_TOP Public

    Multi-Channel Memory Controller / Write Engine — Full RTL-to-GDSII physical design in 45nm CMOS using Cadence Innovus, Genus & Tempus. 64K+ std cells, 48 macros, 200 MHz timing closure.

    Tcl