This project implements a basic Neural Network hardware accelerator using Verilog HDL. The design demonstrates how neural network computations can be executed in parallel using FPGA-style hardware architecture.
- Multiply Accumulate (MAC) Unit
- ReLU Activation Function
- Parallel Neuron Layer
- Weight Memory Support
- Simulation using EDA Playground and EPWave
Input data is multiplied with different weights using parallel MAC units. The results are passed through a ReLU activation function to generate the final outputs.
Input → MAC Units → ReLU → Parallel Outputs
- design.sv – Top level module
- testbench.sv – Simulation testbench
- nn_layer.v – Neural network layer implementation
- nn_layer_parallel.v – Parallel neuron architecture
- weights.mem – Weight memory values
- Verilog HDL
- EDA Playground
- EPWave
Input = 5 Weights = 2, 3, 4, 5
Outputs:
- o1 = 10
- o2 = 15
- o3 = 20
- o4 = 25