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    • Altera Agilex 5 Ethernet System Example Design
      SystemVerilog
      Other
      0001Updated May 11, 2026May 11, 2026
    • Official Intel SOCFPGA Arm-TF repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early access without official cust…
      C
      Other
      171809Updated May 9, 2026May 9, 2026
    • Altera Agilex 5 E-Series GSRD
      SystemVerilog
      Other
      4400Updated May 8, 2026May 8, 2026
    • Nios V Processor example designs targeting Altera Agilex 3 Development Kit
      C++
      Other
      0100Updated May 8, 2026May 8, 2026
    • settings

      Public
      Contains configuration files and scripts for the altera-fpga Github site
      2001Updated May 8, 2026May 8, 2026
    • Hardware and software collateral for altera-fpga developer website
      HTML
      1400Updated May 6, 2026May 6, 2026
    • Example Design that shows how to leverage R-tile AvST PCIe CII Interface to display Vital Product Data Capability
      SystemVerilog
      0100Updated May 4, 2026May 4, 2026
    • Linux development repository for socfpga
      C
      Other
      315286012Updated Apr 22, 2026Apr 22, 2026
    • Altera Agilex 5 HPS-to-FPGA Interface Demos
      Tcl
      MIT No Attribution
      3810Updated Apr 17, 2026Apr 17, 2026
    • Altera FPGA Real-Time Meta Layer
      BitBake
      Other
      0000Updated Apr 17, 2026Apr 17, 2026
    • NVIDIA Holoscan Sensor Bridge - Bring Your Own Sensor (BYOS) over Ethernet
      C++
      Apache License 2.0
      24000Updated Apr 16, 2026Apr 16, 2026
    • Altera Agilex FPGA Drive Controller System Example Designs
      VHDL
      Other
      0300Updated Apr 15, 2026Apr 15, 2026
    • Altera Modular Design Toolkit
      Tcl
      Other
      0400Updated Apr 14, 2026Apr 14, 2026
    • Nios V Processor example designs targeting Altera Agilex 5 Development Kits
      C
      Other
      1400Updated Apr 14, 2026Apr 14, 2026
    • Altera Agilex 3 C-series GSRD
      Makefile
      Other
      1000Updated Apr 8, 2026Apr 8, 2026
    • Meta Altera FPGA Yocto Layer
      BitBake
      0001Updated Apr 8, 2026Apr 8, 2026
    • Shell
      MIT License
      71620Updated Apr 8, 2026Apr 8, 2026
    • This repository contains Yocto Project application and customization meta layer for GSRD(Golden Software Reference Design)
      BitBake
      MIT License
      131632Updated Apr 8, 2026Apr 8, 2026
    • Altera Stratix 10 GSRD
      Tcl
      Other
      0000Updated Apr 7, 2026Apr 7, 2026
    • Altera Arria 10 GSRD
      Tcl
      Other
      1100Updated Apr 7, 2026Apr 7, 2026
    • Altera Agilex 7 F-Series GSRD
      Tcl
      Other
      0000Updated Apr 7, 2026Apr 7, 2026
    • Official Intel SOCFPGA U-Boot repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early access without official cust…
      C
      Other
      158121010Updated Apr 7, 2026Apr 7, 2026
    • Agilex 7 F-Tile 1588 25G Multi-Channel QoS System Example Design
      SystemVerilog
      Other
      0000Updated Apr 6, 2026Apr 6, 2026
    • Nios V Processor example designs targeting Altera Agilex 7 Development Kits
      SystemVerilog
      Other
      0000Updated Mar 20, 2026Mar 20, 2026
    • Altera Agilex 7 PTP System Example Design
      SystemVerilog
      0200Updated Mar 9, 2026Mar 9, 2026
    • C
      0300Updated Mar 1, 2026Mar 1, 2026
    • This is a software reference code to implement the FPGA remote debug feature. User will compile the reference code into a user space application which exchanged…
      C
      BSD 3-Clause "New" or "Revised" License
      81521Updated Feb 28, 2026Feb 28, 2026
    • 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 3 Devices
      Tcl
      Other
      0000Updated Feb 18, 2026Feb 18, 2026
    • Agilex 5 PTP System Example Design
      SystemVerilog
      Other
      0000Updated Jan 30, 2026Jan 30, 2026
    • libfcs

      Public
      Altera FPGA Crypto Services Library
      C
      MIT No Attribution
      2001Updated Jan 9, 2026Jan 9, 2026
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