All

117 repositories

verilator
Public
Verilator open-source SystemVerilog simulator and lint system
SystemVerilog
•
Other
•810•43•0•0•Updated May 11, 2026May 11, 2026
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•66•405•95•11•Updated May 11, 2026May 11, 2026
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•66•29•147•51•Updated May 11, 2026May 11, 2026
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•7•9•0•0•Updated May 11, 2026May 11, 2026
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•87•138•88•25•Updated May 11, 2026May 11, 2026
chisel
Public
Chisel: A Modern Hardware Design Language
scala chip-generator chisel
scala chip-generator chisel rtl chisel3 firrtl verilog
Scala
•
Apache License 2.0
•650•4.7k•352•150•Updated May 9, 2026May 9, 2026
rocket-pcb
Public
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
•
Apache License 2.0
•4•17•0•1•Updated May 9, 2026May 9, 2026
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•43•42•57•16•Updated May 9, 2026May 9, 2026
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•93•375•44•23•Updated May 8, 2026May 8, 2026
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•102•150•209•70•Updated May 8, 2026May 8, 2026
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•27•48•16•10•Updated May 8, 2026May 8, 2026
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•103•337•33•9•Updated May 8, 2026May 8, 2026
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Window…
parser linter preprocessor
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
•
Apache License 2.0
•79•460•47•0•Updated May 8, 2026May 8, 2026
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. U…
serialization listener systemverilog
serialization listener systemverilog ieee-standard vpi-api vpi-interface
C++
•
Apache License 2.0
•42•255•14•0•Updated May 8, 2026May 8, 2026
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•14•49•20•3•Updated May 7, 2026May 7, 2026
caliptra-infra
Public
Various tools used for Caliptra's Continuous Integration flows
SystemVerilog
•
Apache License 2.0
•6•3•6•2•Updated May 6, 2026May 6, 2026
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv
generator spike riscv testsuite rvv
Go
•
Apache License 2.0
•36•111•15•2•Updated May 6, 2026May 6, 2026
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•34•22•17•10•Updated May 5, 2026May 5, 2026
t1
Public
Scala
•
Apache License 2.0
•43•314•19•29•Updated May 5, 2026May 5, 2026
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•31•64•25•18•Updated May 2, 2026May 2, 2026
sv-tools
Public
A SystemVerilog toolchain / suite, encompassing a number of open source tools for working with SystemVerilog and UVM
Apache License 2.0
•0•9•0•0•Updated May 1, 2026May 1, 2026
guineveer
Public
https://chipsalliance.github.io/guineveer/
C
•
Apache License 2.0
•4•8•0•0•Updated Apr 27, 2026Apr 27, 2026
caliptra-web
Public
Python
•
Apache License 2.0
•7•1•0•0•Updated Apr 23, 2026Apr 23, 2026
rocket-chip
Public
Rocket Chip Generator
scala rocket-chip chip-generator
scala rocket-chip chip-generator chisel riscv rtl
Scala
•
Other
•1.3k•3.8k•260•69•Updated Apr 21, 2026Apr 21, 2026
caliptra-ureg
Public
Rust
•
Apache License 2.0
•6•9•1•2•Updated Apr 20, 2026Apr 20, 2026
caliptra-lwip
Public
C
•
Other
•0•0•0•0•Updated Apr 20, 2026Apr 20, 2026
firtool-resolver
Public
Shell
•2•5•0•3•Updated Apr 16, 2026Apr 16, 2026
chips-alliance-website
Public
SCSS
•
MIT License
•7•5•8•2•Updated Apr 16, 2026Apr 16, 2026
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•25•8•37•1•Updated Apr 7, 2026Apr 7, 2026
caliptra-cfi
Public
Code-flow Integrity module to mitigate glitches and fault injections
Rust
•
Apache License 2.0
•5•4•2•0•Updated Apr 6, 2026Apr 6, 2026

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CHIPS Alliance

All

All

117 repositories

verilator

Caliptra

caliptra-mcu-sw

sv-tests-results

caliptra-rtl

chisel

rocket-pcb

caliptra-ss

sv-tests

caliptra-sw

i3c-core

Cores-VeeR-EL2

Surelog

UHDM

adams-bridge

caliptra-infra

riscv-vector-tests

caliptra-dpe

t1

firrtl-spec

sv-tools

guineveer

caliptra-web

rocket-chip

caliptra-ureg

caliptra-lwip

firtool-resolver

chips-alliance-website

tac

caliptra-cfi

All

All

Repositories list

117 repositories